Serially connected LED lamps control device

ABSTRACT

The present invention discloses a serially connected LED lamps control circuit device, which is applicable for an integrated circuit and has the following three features: using a buffer circuit to increase the DATA and Clock lines to extend the distance between a plurality of serially connected devices, delaying half cycle of the timing of the DATA line to enhance overall system stability, and adding an internal latch signal generate circuit to simplify the requirements for external connections.

FIELD OF THE INVENTION

The present invention relates to a serially connected LED lamps controlcircuit device, which is applicable for an integrated circuit andcharacterized in its using a buffer circuit to increase the DATA andClock lines to extend the distance between a plurality of seriallyconnected devices, delaying the half cycle of the timing of the DATAline to enhance overall system stability, and adding an internal latchsignal generated circuit to simplify the requirements for externalconnections.

BACKGROUND OF THE INVENTION

The application of LED becomes popular, and the progress of LEDbrightness also promotes an extensive use of LEDs. Based on years ofexperience on research, development and selling of the LED products, theinventor of the present invention has developed a control device forimproving system stability as well as greatly simplifying the systemwiring.

The design of serially connected LED lamp control device is mainlyapplied for the occasion of connecting a series of LED lamps, and eachLED lamp is controlled effectively and independently.

Three traditional methods for controlling the serially connected LEDlamps are described as follows:

The first design uses a control box to control all lamps and an electriccable to connect each of the LED lamps. The cost for such method islower; however, if the lamps are farther apart from each other or evenlydistributed or arranged, then the cost of the electric cable is veryhigh. Furthermore, since the length for each cable is not the same,which will cause tremendous difficulty for mass production andinstallation. Therefore, this design was adopted only at its earlystage, but is seldom used thereafter because of its disadvantages.

The second design refers to a fixed address serial connection, of whicha control circuit is installed in each lamp and a fixed address ID isassigned to each lamp, such that the system can operate as long as thepower supply and the signal line are connected. Such system is simpler,but it has several drawbacks. Since each lamp requires a controller,therefore the cost is higher. In addition, each lamp requires adifferent ID, and thus making the manufacturing more difficult.Furthermore, it is necessary to change the ID of the spare parts forrepair and maintenance purposes, thus causing some troubles.

The third design adopts a serially connected control circuit, whichsubdivides the controller as described in the abovementioned system andinstalls some part of the circuit in the lamp, and then all lamps areserially connected by an electric cable. Therefore, each time isseemingly identical and thus this design can simplify the level ofdifficulty for wiring, installing and maintaining the whole system.

Please refer to FIG. 7 for the block diagram of the foregoing thirdconnection method. There are only 5 lamps 101 a˜101 e shown in thefigure, and a minimal quantity of signal wires 102, 103 is required forthe system, which includes a total of six lines such as a DAT, a Clock(CLK), a latch signal (STB), an output enable (OE) for controlling thebrightness, a power supply (VDD) and a ground (GND) lines. Each lampunit 101 a˜101 e uses the same line to connect the signal 103. Pleaserefer to FIG. 8 for the internal structure of the lamp units 101 a˜101 eas depicted in FIG. 7, which comprises 4 sets of circuits fordescription. In actual practice, the number of circuits depends on theactual need. In FIG. 8, the signal group 210 is an input end, and thesignal group 211 is an input end of another signal, and four sets ofD-type latches 203 a˜203 d constitute a set of S-R shift registers andare driven by the external clock signal CLKI to save the external dataDATI into the latches 203 a˜203 d in the proper order. In the meantime,the internal data are sent to the next lamp through another data lineDATO. After the data is shifted to a fixed address, the external latchsignal STB 1 will be outputted from four sets of D-type latches 203a˜203 d to another set of D-type latches 203 a˜202 d and then sent tothe LED driver circuit 201 to drive the external LEDs 213 a˜213 c. Thebuffers 204, 205, 206, 207 act as the buffers for the output of the CLKsignal and data, the output of DATO latch signal, the output of STBO andthe brightness output OEO respectively. The four connected signals DAT,CLK, STB and OE are the minimum requirement for such system. If there isan additional required function, the quantity of connecting wires willbe increased. In view of the design that subdivides the central circuitto each lamp, the level of its originality is not high.

Since the method adopted by the foregoing method requires the connectionof many circuits, and the lengths of the external connecting cables aredifferent, and different lots of ICs have a slight difference such thatthe signal transmission error may occur easily (which will beillustrated by FIGS. 4 to 6), therefore the inventor of the presentinvention based on years of experience on designing and manufacturingsimilar system to invent and develop the control device in accordancewith the invention to greatly improve the overall system stability aswell as greatly reduce the required number of circuit connections.

SUMMARY OF THE INVENTION

Therefore, the primary objective of the present invention is to providea serially connected LED lamps control circuit device, which isapplicable for an integrated circuit and has the following threefeatures: using a buffer circuit to increase the DATA and Clock lines toextend the distance between a plurality of serially connected devices,delaying the half cycle of the timing of the DATA line to enhanceoverall system stability, and adding an internal latch signal generatedcircuit to simplify the requirements for external connections.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the method for connecting the LEDsaccording to the present invention.

FIG. 2 is a structural diagram of the present invention.

FIG. 3 is a timing diagram of the present invention.

FIG. 4 is an illustrative diagram of the principle of delaying the datafor a half cycle according to the present invention.

FIG. 5 is another illustrative diagram of the principle of delaying thedata for half cycle according to the present invention.

FIG. 6 is a timing diagram of the clocks as depicted in FIGS. 4 and 5.

FIG. 7 is a block diagram of the method for connecting the LEDsaccording to the prior art.

FIG. 8 is a structural diagram of the LED lamp unit as depicted in FIG.7 according to the prior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Please refer to FIG. 1 for the block diagram of the method forconnecting the LEDs according to the present invention. In FIG. 1, thewhole circuit device only requires two signal lines: CLK and DAT inaddition to the power supply VDD and ground GND. There are five lampunits 301 a˜301 e, an input end 302, and an output end 303. The deviceis very simple and neat, which consists only four circuits between alllamps.

FIG. 2 illustrates the structure of the present invention. There are twodifferences from the traditional structure as depicted in FIG. 8, suchas a D-type latch 403 e is installed in front of the data output DATOfor the inverted clock synchronization, which can delay the data forhalf a cycle; and a clock loss detect circuit 408 is added. If a dataDATI and the clock 502 as shown in FIG. 3 are sent, the clock CLKI andthe clock 501 as shown in FIG. 3 will stop for a while, and then TIos504 as shown in FIG. 3 and the circuit 408 will automatically generate alatch signal 418, and a latch signal 417 is obtained from the latchsignal selector 407 and sent to another set of D-type latches 402 a˜402d to latch the output data 415 of the original S-R shift register 403a˜403 d to generate an LED control signal 414, and then the LED drivercircuit 401 drives the LEDs 419 a˜419 c. Therefore, a connecting lineSTB can be reduced. The latch signal select circuit 407 is added toprovide circuit flexibility, and a system designer can select to use aninternal or an external latch signal, and such choice is controlled bymode wire connection STB mod411, which is not essential to the presentinvention.

The clock buffers 404, 405 as shown in FIG. 2 has the same functions asthose as shown in FIG. 8.

The timing diagram as shown in FIG. 3 illustrates the operatingprinciple of the clock detect circuit 408 as shown in FIG. 2. Ingeneral, the timing of the TIos is preferably 20 μs˜100 μs, but suchvalues are not limited to these settings depending on different designsof the whole system.

FIGS. 4 to 6 illustrate the principle and significance of the principleof delaying the data for half cycle. The data latch 610 a of the firstdevice as shown in FIG. 4 latches the data 603 of the output DAT 602 ofa previous set of latches at the positive edge 611 of the clock CLK 601,and the signal 614 drives the next glatch 610 b to operate when theclock CLK 601 is inverted to 601 a as to delay the output data 603 halfcycle and becomes the next output 604. Therefore, the data latch 610 cof the next device as shown in FIG. 5 is buffered, and the rising edges620, 621, 622 of the clock 605 latches the output 604 of the previousdevice as shown in FIG. 4. For each input data, the latch 610 a, 610 cwill latch the data after the data is stable and at the middle sectionbefore/after the data is changed. Therefore, such arrangement can assurea very accurate data DAT fetched by each clock CLK.

In the timing diagram as shown in FIG. 6, the shaded area is an unstabledata area, and the cause for the unstable area resides on that eachbatch of ICs will output data DAT faster or slower than the output ofclock CLK due to different manufacturing processes. Since each digitalsignal is either “0” or “1”, a slope will be produced because thecapacitors and resistors of the circuit are affected. Due to differentmanufacturing process, the internal latch 601 a, 601 c of each IC has adifferent voltage (approximately ±20% VDD) for fetching data, which willalso produce a timing difference.

As to the traditional design illustrated in FIG. 8, the output of theclock CLK and the data DAT have very close timing (within severalnanoseconds or tens of nanoseconds). Once the ICs from different batchesare connected, it is easy to generate data error, and such error has notmuch effect within the same circuit board, but when two differentdevices with a distance of over 100 mm apart, then the effect willbecome very large. For example, the data DAT 603 fetched by the clockCLK 605 of the timing 631, 632 as shown in FIGS. 4 to 6 falls into theunstable area and the correct data cannot be fetched 100%.

Further, the brightness control instruction for the brightness functionoriginally controlled from the outside can be sent from a serial signaland processed by an internal logic circuit as to reduce another circuitOE as shown in FIG. 8. However, such technology is not special, and willnot be described here.

In view of the description above, the control device in accordance withthe present invention can greatly improve the system stability and lowerthe cost for the whole device. With the IC design, the volume can begreatly reduced, and thus the system with serially connected LED lampsshould be the mainstream in the coming years.

1-2. (canceled)
 3. A serially connected LED lamps control devicecomprising: a plurality of shift registers, and an LED driver circuit aninternal latch signal is used to produce a circuit to reduce thequantity of connections and a plurality of circuits capable of delayingan output data for half cycle as to improve the stability of a system,wherein said LED driver circuit comprises a D-type latch being installedin front of said data output for an inverted clock synchronization andcapable of delaying an outputted data for half cycle, and a clock lossdetect circuit added to said control device, such that when said data issent and the clock is stopped for a predetermined time, said circuitautomatically generates a latch signal, and said latch signal isobtained by a latch signal selector and set to another D-type latch tolatch the output data from said original S-R shift register as togenerate an LED control signal and said LED driver circuit drives saidLED lamps, thereby a connecting line is reduced; wherein said latchsignal select circuit adds a circuit flexibility such that a systemdesigner selectively adopts a desired internal and external latch signalas needed.
 4. (canceled)